Binary-coded flip-flop counters



United States l 2,853,238 Patented Sept. 23, 1958 Fice BIN ARY-CODEDFLIP-FLOP COUNTERS Robert Royce Johnson, Pasadena, Calif., assignor, by

mesne assignments, to Hughes Aircraft Company, a corporation of DelawareApplication December 20, 1952, Serial No. 327,131

12 Claims. (Cl. 23S-92) plication, Serial No. 245,860, entitledHigh-speed Flip- Flop Counter,.by Eldred C. Nelson, filed September 10,1951, discloses a binary counter wherein all flip-flops aretriggered.simultaneously in response to count pulses applied inYparallel to a plurality of and circuits, one for 'each flip-flop. Eachofthe and circuits is controlled by voltage-state signals derived fromthe conduction states of each of thetprecedingiip-fiops in the counterchain.

`Application Serial No. 245,860 has been assigned of record to theassignee of .this application.

AThe counterndescribed 1in the first copendingapplica- `tion may; `bedistinguished from prior-art binary counters in that the flip-flops arenot connected in cascade The term cascade is utilized to indicatethat.each flip-flop in the counter chain is triggered by a carry pulseproduced 1by the preceding flip-flop, as it is triggered from al-representing state to a O-representating state.

caded type of fiip-flop counter the count pulses are api plied to thefirst flip-flop in the chain and carry pulses In the ,cas-

are then propagated through the counter. A settling time must be allowedbetween the count pulses to permit the counter to assume acount-representing stable state before the next pulse is applied. Thissettling time is equal to N times the time of pulse propagation bejtweentwo flip-flops, where N is the total number of fiipops.

One ofthe features of the counter shown in the first application, then,is `that it may be operated at approximately N times the speed of thecorresponding prior-art countergN again being the number of fiip-fiops.

The second copending U. S. patent application, Serial No. 327,567, nowPatent No. 2,816,223, entitled Binary- Coded, Flip-Flop Counters, byElred C. Nelson, filed December 23, 1952, extends the principlestaughtin the first copending application to all binary-coded fiip-fiopcounters, with the introduction of a novel transformation theory.Copending application Serial No. 327,567, now Patent No. 2,816,223 hasalso been assigned of record to the assignee of this application.According to this transformation theory, there are three basic types ofVtransformation functions `which may be utilized to define the sequenceof stable states of a flip-flop. The first type of transformationfunction is referred to as a setting transformation `function anddefines the conditions for setting the flip-flop to be controlled to a1-representing state or to a -representing state. The second type oftransformation function is referred to as a changing transformationfunction and defines the conditions for changing the ip-flop tositsopposite representing state i. e. from means of a` novel simplificationtechnique.

a 1-or-0 representing state to a O-or-l representing state. The thirdtype of transformation function is referred to as a partial-changingtransformation function and defines either the conditions for changingthe associated flip-flop from a l to a 0 stable state, or the conditionsfor changing the associated fiip-flop from a 0 to a 1-representingstate. Two partial-changing transformations are required to completelydefine the changing transformations of a flip-flop; one defining theO-to-l change and the other the l-to-O change. The logical sum of twopartial-changing transformations -is equal to the complete changingtransformation.

For example, a partial-changing equation for triggering a fiip-flop tothe true state'may be written as 1F=F.G. where 1F=a signal fortriggering the F flip-flop from the false state to the true state of theflip-flop;

F=the false state of operation of the F fiip-op;

G=a first signal from a source external to the F tiipflop; and the dotf.) between F and G represents an and proposition in which F and G haveto be true in order for a 1F triggering signal to be produced.

Similarly, a partial-changing equation for triggering the F fiip-fiop toits false state may be written as OF :F .H where OF= a signal fortriggering the F Hip-flop `from the true state to the false state of thefiip-op;

H=a second signal froina source external to the F flip-hop.

The partial-changing functions set forth above may W be combined intoone function completely listing the changing transformations for theFflip-fiop. This changing transformation may be Written as Cf=asignalfor changing the F fiip-fiop from the false state to the truestate of the flip-flop .or for changing the F flip-flop from the truestate ofthe false state of the flipop.

In addition to the three basic types of transformations, a fourth typeof transformationis described in the second copending application; thefourth type being referred to as a simplified partial-changingtransformation, since it is derived from a partial-,changingtransformation by The four types of transformations are re-introduced inthe present specification andvexplained briefiy, reference being made tothe second copending application for further details.

In both of the copending applications the particular counting code andcycle which is desired is first determined, and then the transformationfunctions defining this code and cycle are derived. While fo-r eachcounter thus defined, there is a set of transformation functions whichprovides the simplest gating circuits and allows minimization of power,there is no assurance that the particular code which has already beenselected is the simplest to mechanize, or that the iii-p-fiops providingvoltage-state signals for controlling the gating circuits are evenlyloaded. In binary fiip-fiop counters of the type described in the firstcopending application, for example, the and gating circuit controllingthe Nth fiip-flop (Where N is any integer) has N -1 input terminals,necessitating a corresponding number of diodes, Where diode and circuitsare utilized, or a corresponding number of control grids, wherevacuum-tube and circuits are utilized. In addition to the complexity ofthe gating circuits in the binary counter, the flip-flop loaddistribution is unbalanced` since one of the ffip-fiops produces avoltagestate signal which is utilized to control N*l gating circuits,whereas another has no load whatsoever.

According to the present invention, the transformation functions arederived first according to principles which insure that the gatingcircuits will be simple and that the ip-fiop load will be evenlydistributed. The even distribution of the load results from the factthat each flip-flop has its output voltages introduced to substantiallythe same number of input terminals in the counter as the output voltagesof the other flip-tiops. Another way in which the load can be consideredto be evenly distributed is that each input terminal in the countergenerally has introduced to it only the output voltage from one of theHip-flops in the counter. Having thus defined a simple, balanced-load,flip-flop counter; the code and counting cycle are determined. A counterhaving any cycle desired may be defined in this manner, the code being,in effect, predetermined by the transformation functions, Which define aset of simple gating' circuits and place a balanced load on theflip-Hops. By code is meant the interrelationship between the differentip-fiops in the counter to obtain the desired count. Thisinterrelationship can be set forth by logical equations for each counterincluded in the invention, as will become more apparent subsequently.

The basic embodiment of the present invention cornprises: a plurality offlp-fiops producing voltage-state signals corresponding to their stablestates, respectively; and a transformation matrix responsive to thevoltagestate signals and to applied counting pulses for producingcontrol signals which control the sequence of stable states of theflip-Hops. The transformation matrix is mechanized according to a set oftransformation functions, one for each flip-op in the counter. Thesefunctions are derived according to principles which insure that thegating circuits in the transformation matrix will be simple and that theload placed upon the ip-ops will be evenly distributed.

Accordingly, it is an object of the present invention to provide abinary-coded ip-tiop counter mechanized according to a set oftransformation functions defining simple gating circuits and providing abalanced load for the ip-tiops in the counter.

Another object of the present invention is to provide a high-speedcounter in which pulses to be counted are applied to each of a pluralityof Hip-flops through a single gating matrix; the counter including aminimum of gating circuits.

A further object of the invention is to provide a binarycoded flip-flopcounter wherein a transformation matrix is utilized to produce controlsignals determining the sequence of the counter, the transformationmatrix being responsive to voltage-state signals produced by theflipflops and to the applied counting pulses and being mechanized insuch a manner as to provide a balanced load for the Hip-flops. Bysequence of the counter is meant the pattern of the different flip-flopsin the counter to represent different numbers. For example, theflip-flops in the counter may have a first pattern of operation torepresent a rst number such as "1 and may have a second pattern ofoperation to represent a second number such as 2, The changes in thepattern of operation of the flip-Hops in the counter from each number tothe next may be considered as the sequence of the counter.

The novel features which are believed to be characteristic of theinvention, both as to its organization and method of operation, togetherwith further objects and advantages thereof, will be better understoodfrom the following description considered in connection with theaccompanying drawings, in which several embodiments of the invention areillustrated by way of examples. It is to be expressly understood,however, that the drawings are for the purpose of illustration anddescription only, and are not intended as a definition of the limits ofthe invention.

Fig. 1 is a block diagram of the basic embodiment" of the presentinvention;

Fig. 2 is a schematic diagram of a scale-of-l() binarycoded counter,employing a scale-of-S binary-coded counter;

Fig. 3 is a schematic diagram of a scale-of-8 counter;A

Fig. 4 is a schematic diagram of a scale-of-16 counter; and

Fig. 5 is a schematic diagram of a scale-of-32 counter.

Referring now to Fig. 1, there is shown one embodiment of a binary-codedcounter according to the present invention in which pulses Cp to becounted are applied to a transformation matrix which produces controlsignals for actuating a plurality of flip-flop stages A, B, and N, whereN is utilized to indicate that any number of stages may be included.

Before proceeding to consider specific counters which are mechanizedaccording to the present invention, it is necessary to consider thenovel principles which make it possible to select a set oftransformation functions that define a minimum amount of gating circuitsand provide balanced loading for the fiip-flops.

The notation which is utilized in the explanation which follows isconsistent with that utilized in the second copending application. Thechanging transformations which are considered below are represented by Cfollowed by the letters a, b, ticular flip-Hop which is controlled. Thepartial-changing transformations are represented in the same manner' asthe corresponding changing transformation with the addition of thenumber 1 or 0 indicating whether the flip-flop is changed to l orchanged to 0. Thus, the partial-changing transformation CbO indicatesthe conditions under which flip-dop B is changed from a stablestaterepresenting binary l to a stable-state representing 0. The settingtransformations are designated by the symbol S plus the letters a, b, nand either l or 0 indicating whether the fiip-op is set to l or set to0.

It should be appreciated that the operations of flipflops may becontrolled by setting functions as well as changing functions. Forexample, the flip-Hop F is triggered to its true state for the condition1F=F.G only when I-I and G are simultaneously true. A changing functionindicates. therefore, when a triggering signal is introduced to aflip-op. On the other hand, a setting function indicates when a ip-fiopremains in its present state of operation. For example, for a conditionSal=B, the A flip-flop remains in its true state as long as B remainstrue. When B becomes false, the A flipflop becomes triggered to itsfalse state.

In the second copending application it is established that a 0-to1partial-changing transformation in the form: Cf1=-.Q(A, N) may bereduced to the simplified partial-changing transformation: 1F=Q(A, N),where F is the complementary signal produced by any of the flip-flops Athrough N and Q(A, N) is any function of the other flip-dop signals,where (A, N) identifies Hip-flops and Q refers to flip-flop output. In asimilar manner it is established that the 1-to-0 partialchangingtransformation in the form:

may be reduced to the simplified partial-changing transformation:0F=Q(A, N).

It is also pointed out in the second copending application that eachchanging transformation is the logical sum of the correspondingpartial-changing transformations. Thus, Cf=Cf1iCf0. It follows, then,that a changing transformation in the form:

or n indicating the par-- tnay be reduced to. thesimplifiedpartial-changing transformations:

'i Thesimplest gating circuit is onewhich isutilized to Ca=Cp,' where"'Ca=a changing function' to indicatea triggering of the Aflipiilopfrom'one .state of operation tothe other;

`..Cp=a'c1ock signal.

yIf theJA-ipfflop:and:thef'Bfflipiflopwvere included in Ia counter*`having only/two flip-flops,x`Ca=Cp might `#representr axsimplied form'ofAs will be seen, "the proposition ---i-A--l-'B-i-A'B is always "true'since itrepresents the only possible combinations for operation of theA and B flip-flops. From this, it can be seen that counter, the maximumcount of the counter is only a decimal value of 2 when. each flip-op istriggered v, of, pperation. If G ,isproduced bythe complementarydirectly by the clockpulse andithe' count is initiated from a valueof 1. For examplegtheip-ops A and B may be included in a counter suchthat each Hip-flop is triggered by the clock pulse from one state ofoperation to the other. Thus, Car-,Cp and .Cb=Cp. By this arrange 1occurrenceofparticularioutput voltages from at least one other flip-Hopin the counter. In otherzwordspcertain of the ip-flops must beresponsive to signals representing` the voltage states of at least oneother flip-flop in the counter.

As will beiseenmore clearly subsequently, certain ipflops in eachYcounter may betriggered by each clock pulse so as to' be responsive tothe voltage states of nonel of the other flip-flops in the counter. Eachof the other flip-flops in the counter is generally -responsive to thevoltage state of only one other flip-flop in the counter. In this way,counters having balanced loads on the different'liip-ops in the counterare obtained.

it `willbe established that any gating circuit responsive to only :oneflip-flop signal may be denedbya changing function in thev form:Cf=(F.G-}F.H)'.Cp, where G and H `arevoltage-state signals which may beproduced bythe samev section of a flip-flop, by different sections ofthesame flip-liep, or bydifferent flip-Hops.

l.If G and H are produced by the same section of a ilip-op, that is`G=H, it is apparent that the function Cf may be lreduced to one in theform: Cf=G.Cp. If H is produced by the complementary section of ipop G,

.cf becomes; cf=(G+F.).cp; which, it 4will be :ashownymayabe replacedVby the setting function:

By complementary section of a ip-op isintended to mean the' other of thetwo states-of operation of the flip-flop. For example, if the firstsection of the G flip- -flop is considered as. G (or` true), thecomplementary usectionofathe flipfop would be the G (or false) statewhich Vmay be'replaced by the setting`"'function:

sf1=sfo=tcp Finally, if `G andv H are Vsignals produced by different`hip-flops, thentfunction.CJS may be reduced tolthe` simplifiedrparti'al-,chan/gingfunctions: Q lF`=fG.Cp; ,0F.-.H.Cp; this case beingconsidered..as .pmvidinga rnixed function, since thecontroloflthe,ipfopRis. dependent upon the signals of two differentflip-flops.

After ip-opFis.y operated y:upon according to a changing functionC;f,-.its` output signal F becomes the signal F deined by the function:Ff-r.F.Cfl-F.Cf,lindi eating that F is the complement bf previoussignalF after flip-Hop F is triggereda's required by the condition: Cf=1; andthat F is equal to previous signal F when Cf is equal to 0 (Cf=`l)andflip-op F is not triggered. Substituting for Cfand Cf, F becomes:F'='F.(F.G+F.H)+F.(F+).

.-.=.F.G+F.

wherefsignal'Cp is jor'nitted# sincef`fF'-represents a voltagestatesignal. f

When G and H arethe vsame variable, F is in the form:

Y lvariablesg` F.he con 1es equaLtomGa when H ,is .replaced by G, orequal to H when G. isfreplacedrbyiathusestabf lishing the fact that the,changing function:

mined from a stable,.wherein.a set of reference counts are transformedinto a second set of counts according `to".4 thetransformationsfunctions. Lz-'Eon convenience .;,the

reference counts may befin.asconventionalbinaryccode, although any codemay be. used. In Table I below, columns A and B represent conventionalbinary variables and columnsAV and B' represent the transformation ofthese variables.according to thei functions: t

Table l UAH B' Sequence Referring now to Table? I,v it will be notedneither A nor B is changed after the reference count 00 represented bythe condition: 23:1, and consequently the counter locks at 00; thus,,the letter L is placed opposite to count 0G.

Flip-flop A is triggered after the count: 0l (A.B=1), transformingthe-count 01 vtolthe count 1l which may be considered as the firsttransition in a cycle of 3. Fliptipp Bis.,niggeredgaftenthe count11,,since A is equal to 1; and thus,'the second count in the scale-of-3sequence is 10. Finally, both flip-Hops AI and B are triggered afterCa=B.Cp represented in Table II.

` Table II A B A' B Sequence o o o o L o.1 1 o 1 1 o 1 1 n 1 1 o 1 aSimilarly, complementing the signals of either of flip-Hops A or B, orboth Aand B; provides the functions:

where signals A and are complemented, the counting cycle being shown inTable III:

Table Ill A B A' B Sequence vwhere signals Band B are complemented, thecounting cycle being shown in Table 1V:

Tabtelv A B A' B' Sequence where both flip-flop A and B signals arecomplemented, the counting cycle being shown in Table V:

Table V A B A B' Sequence 0 0 0 1 1 0 1 1 0 2 1 o o o s 1 1 1 1 L Thereare four other sets of functions.v andcorrcsponding sequence tableswhich are obtained by complementing the signals in the permutated setabove.

As will be seen, a considerable number of sets of transformations may beobtained for each counter even when only two flip-ops are in thecounter. It may be shown from what has been considered that each set oftransformations may be considered to represent N' X 2N, similar setsthat may be derived therefrom by permutating or complementing certainflip-flop signals Where N equals the number of flip-flops in the counterrepresented by the set of transformations. For example, by formulaN'XZN, it will be seen that eight different sets of transformations maybe obtained for a counter having N=2 flip-flops. Four sets oftransformations have been set forth above. It is believed that a personskilled in the art would be able to derive the other four sets oftransformations from the above discussions and from the four sets oftransformations already set forth in the specification. Eliminating allof the sets of functions which may be obtained by permutating orcomplementing the variables in the basic functions, the following arethe basic functions for two flip-flop counters, according to the presentinvention:

The count sequences for these functions are tabulated in Table VI,below:

The operation of the A and B flip-flops in accordance with the logicalequations of set l may be seen from the following discussion. Assumethat the A flip-flop is initially false and the B flip-flop is true.This corresponds to a value of l, as may be seen from vertical column 1in Table 6. Since only one of the A and B hip-flops is true, the A ip-opbecomes triggered upon the introduction of the rst clock signal Cp. Thiscauses the A iiip-op to change from a false state to a true state.However, the B ip-flop dies not become triggered since it can betriggered only when the A ip-op is in its true state before theintroduction of the clock pulse Cp. Because of this, the A and Bflip-flops are both in their true state after the introduction of therst clock signal Cp. This corresponds to a decimal value of 2 invertical column 1 of Table VI.

Since both A and B are true, the operation of the A ip-op cannot bechanged upon the introduction of the next clock signal Cp. However, theoperation of the B ip-op changes from a true state to a false statesince the A flip-flop is true. The respective operations of the A and Bllip-ops in their true and false states correspond 9 to a decimal valueof 3" in vertical column (1) of Table VI.

Upon the introduction Vof the next clock signal Cp, the A flip-flopchanges fromY its true state to its false state. The reason for this isthat Vonly one ofthe two flip-flops is true before the introduction ofthe clock signal. At the same time, the B flip-flop changes from a falsestate to a true state since the A flip-flop is true before theintroduction of the clock pulse Cp. When .the A flip-flop becomes falseand the B flip-flop :becomes true, the flip. flops are in a state ofoperation corresponding to a decimal value of l. In this way, the A andB flip-flops return to `their initial state for the commencement of anew count. By such an arrangement, a cyclic count' between l and 3,inclusive, is obtained upon the introduction "of successive clockpulses.

It may sometimes happen'that both A and B are in their false states ofoperation. When this occurs, the operation of the A flip-flop cannotbecome changed because of the requirement that one of the flip-flopsmust be in its true state in order for the A flip-flop to be triggered.The B flip-flop also cannot be triggered since it can be triggered onlywhen the A flip-flop is true. For this reason, the A and B flip-flopsremain locked in their present states of operation. This is designatedby the symbol L in vertical column l of Table VI.

Consider now the second set of logical equations. These may be repeatedas `The A and B flip-flops may be considered to be in their false statefor a decimal value of l, asshown in vertical column 2 of Table VI. Withthe A and B flip-flops in their false statesof operation, the B flip-Hopbecomes triggered to its true state upon the occurrence of the first Cpsignal but the A flip-flop remains false. AT-his corresponds to adecimal `value of 2 in vertical. column 2 of Table VI.

Since only the B flip-flop is true, the second clock signal i causes Ato become triggered true and the B flip-flop to remain true. Thiscorresponds to a decimal `value of 3 in vertical column 2 of Table VI.Because of the true states of both the A and B flip-flops, A remains`true and B becomes triggered to its false state when the third clocksignal Cp occurs. This represents a decimal value of 4 in verticalcolumn 2 of Table VI. The A and B flip-flops return to a decimal valueof 1 upon the occurrence of the next clock signal so as to initiate anew count.

The third set of equations is as follows:

As will be seen, the A and B flip-flops cannot be'triggered when theyare both true or both false. This is indicated by the letters L linvertical column 3 of -Table VI. When A is false and B is true, A becomestrue and B becomes false upon the introduction of the first Cp signal. Areturns to its false state and B returns to its true state uponthe'introduction of the next clockY signal. In this way, the A and Bflip-flops can count only the values of 1 237.

In the fourth'set of equations,

Various sequences of operation are' possible when the A and B flip-flopsare connected in accordance with the fourth set of logical equations.For example, the A and B flip-flops may both be initially false. Thiswould prevent either of the A or B flip-flops from being triggered tothe true state. This is represented by the symbol L in vertical column 4of Table VI.

' flip-flop initially true, as represented by the symbol fl in representawdecimal fvalue of 2. ..2 in .vertical column 4 of Table VI.

the vertical column 4 of Tal-f3 VI. Upon the occurrence of the first Cpsignal, the B ip-op remains true and the A flip-flop becomes triggeredtrue to represent a decimal value of 2 in verticalcolurnn 4 of Table VI.The next clock signal Cp causes both A and B to become false torepresent a decimal value of 3 in vertical column 4 of Table VI. Whenboth A and B become false, the flipops become locked as described above.In this way, the flip-flops count from l to 3 and then cannot return toa value -of l for the initiation of a new count.

A decimal value of l may also `be represented by a true state ofoperation of the A flip-flop and a false state of operation of the Bflip-flop. This is indicated by the symbol 1' in vertical column 4 ofTable VI to distinguish the count from the other counts in the column.Upon the introduction of the first Cp signal, the A flipflop remainstrue and the B flip-flop becomes true to This isindicated at Both of theA f and* B ip-ops then become false when the neXt Cp signal-occurs. lThis is` indicated at 3in vertical column `4 of Table, VI. fflocked intheir false vstates of operation, as described in udetail previously.

The A and B nip-flops then become VIn'rnany cases where there areseveral counting cycles defined by a `set of transformation functions,it is possible to obtain a set of'simplified functions that dene onlyone 'of Y,the"cycles,.;the. other cycle..being eliminated. Thus,

'The simplified functions then define the cycle of Table Table VII A B AB `Sequence U O 1 l l 0 1 1 1 1 1 0 (l 1 3 1 1 1 0 2 It will be notedthat the counter no longer locks at 00, but rather enters into the cycleof 3 by passing through 00 and 11.

,The changing* transformations, above, may now be placed intotheirminimum gating-circuit forms:

1A Cp 1B: Cp (1) Whenever two counters have cycles having no commonfactor, they may be operated simultaneously to provide a cycle equal tothe product of the separate cycles. Thus, the 3 and 4 stable statecounters described above may be operated simultaneously to provide a l2counter,

and the 3 counter may be operated simultaneously with a 2 counter(provided by a flip-flop which is continually triggered) to provide a 6counter. The simplified functions and a cycle table for a scale-of-6counter using the 11 Y simplified 3 counter described above and a thirdfiipop C are shown below:

The simplified set of transformation functions defining the scale-of-6counters may be converted directly to another, equivalent set, bycomplementing the signals of either or both of flip-ops A and B, andthen interchanging the 1 and 0 input functions of the correspondingflipflop. It should be appreciated that this complementation can beperformed mentally and not by any physical structure since it is merelyfor the purpose of obtaining a new set of transformation functions.Thus, when signals of flip-flop A are complemented and the l-and-O inputfunctions for flip-fiop A are interchanged, a first set of complementedfunctions may be expressed as follows:

A second set of complemented functions is obtained by interchanging thel-and-O input functions for flip-flop B in the original set andcomplementing the output signals yof flip-flop B. This provides thefunctions:

Finally, a third set of complemented functions is obtained byinterchanging the l-and-O input functions for both dip-flops A and B inthe original set and then complementing all voltage-state signals. Thisprovides the set:

The fiip-flop signals may, of course, be complemented in the basicchanging functions. Thus, the third complemented set above may lbeobtained by complementing the signals of hip-flops A and B in the basicchanging functions for the original set:

and then simplifying.

It is interesting to compare the counting sequence provided by the thirdcomplemented set of functions with that obtained from the original set.The original set can be repeated as The third complemented set can berepeated as The counting sequence of the third complemented set is shownin Table IX:

. of l in the third complemented set.

If the cycles of the scale-of-6 counters defined by the original set andthe third complemented set are compared in sequence order, the sequencebeing started from counts of lll and 000, respectively, it is noted thatthe counts are complementary. This is shown in Table X:

Table X Original set Third Complemented set Sequence A B C A B C Thecounts of the two sequences bear a complementary relationship becauseythe signals of flip-flops A and B have been complemented to provide theconversion from the first set to the third complemented set, and becauseip-flop C is complemented, in effect, by the shift in the startingcount.

Flip-op C is effectively complemented since it has a true indication fora decimal value of l in the original set and a false indication for adecimal value It should be appreciated that the initial values of the A,B and C flipfiops for cach set are purely arbitrary since the flip-Hopsoperate on a closed loop basis. In a closed loop, the ip-ops count to amaximum value and then return to an initial value at the next clockpulse Cp for the commencement of a new counting cycle. On this basis,the A, B and C flip-flops can all be in their true state for a decimalvalue of l in the original set of transformations and can all be intheir false state for a decimal value of 1 in the third complemented setof transformations. These values are chosen since the A, B and C ip-opsare in complementary states of operation for each value in the originaland third complemented set.

While there are many three flip-flop counters which may be mechanizedaccording to the present inventions, for simplicity, only five basictypes are considered below, illustrating counters having major cycles offour, five, six, seven, and eight, respectively. It should beunderstood, however, that for each of the five counters described, thereare 3 23 others which have the same cycle; and that not all of the basictypes of three flipflop counters are shown. The counters having cyclesof four, five, six, seven, and eight counts are mechanized,respectively, according to the function sets 1, 2, 3, 4, and 5, shownbelow:

1A=B.C'p 1B=A.Cp (3) ;.Cc=,B.C'p

. ,0A=C'.Cp V0B=A.C'p

1B=0p (4) Ca= 0.012; Cc=B.Cp

,0B=A`.Cp

1A=B.Cp 11B- 4.271.011 (5) Cc=Cp A=C.C'p .0B=A.Cp

The sequences of these counters are shown in Table XI:

.T able"` Xl AB C (1) (2) (3) (4) (5) 0 0 0 1 1 L 1 1 0 0 1 1' 2 L s 40. 1 o 2 1' 1 2 5 `011 l2 4"3 3 2 1v o 0 3' 2' 4 L 7 1 o 1 4' 5' 2 5 8 11 0 3 L 5 4 6 1 1 1 4 3' 6 7 3 It will be noted that set l defines acounter having two separate cycles of four counts each; the sequence ofone cycle being Vrepresented by primed numbers. If the. countingsequence is initiated at a count of 000, the counter cycles according toone code; and if at a count of 001, it cycles according to a secondcode. The manner in which the sequence of the counters defined byfunction sets: 1, 2, 3, 4, and are obtained from the corresponding'functions should be apparent from the examples already v"considered,andv further'discussion, therefore, is considered unnecessary.

The five counter vdefined by function set 2, above, mayl be simplifiedby eliminating the. cycle of 2. If counts 000 and 001 .are converted tolll and 110, re-

spectively, a count pulse .signal maybe continuously applied to thelinput circuits of flip-Hops` A and B. The simplified functions andcorresponding transformed counts then are:

A second, simplified ve counter which is very similar to that justdescribedis dened by the functions:

-'Il1is .counter` places a somewhat less load on flip-flop B,..sincesignalaBacontrols the gating of count pulses to only the 0 input circuitof flip-flop C, rather than to both the l and 0 input circuits.

A ten-stable-state counter, utilizing the second simplied ve counter anda scale-of-Z counter operated simultaneously, is shown in Fig. 2.Flip-op D, shown in Fig. 2;-prov'ides the scale-of-Z counter and istriggered continuously by directly appliedcount pulses, Cp.

VCount pulses Cp are also'applied directly to the liinput .,circuitsofflip-flops A, B, and C.

Each of the and.functions` in the defining-set of transformationfunctions is, provided by 1an yand circuit;` "the functions CCp, A.Cp,'and B.Cp being provided by and circuits 210, 220, and 230, respectively.

yCount pulses Cp are applied to one-input terminal of Veach of the andcircuits, since the variable Cp is s in each of the corresponding andfunctions. Signals and . and

i pulse which is applied to the 0 input circuit of ip-op A.

In a similar'manner, and. circuits 220 and 230 provide pulsescorresponding to Athefunctions: A *Cp `and B.Cp, respectively. i v

:The logical equations controlling the operationof the countershowninFigure 2 may be written as follows:

The table representing. the patternsv ofoperation of the A, B, Cand D-ip-.opsfonthedifferent. decimal `values may Abe written as.fo1lows:

Tabla XIMA) :Sequence As will be seen in Table XII(A), a decimal valueof fl may be considered as being represented by true states of operationof the .A andC ip-ops and false states of operation of the B and DHip-Hops. In accordance With the,.logical equations set forth above andythe connections shown-in Figure, 2,.` the B and D flipops are triggered4to their true `state upon the introduction of the first clock signal.The-Aflip-op is triggered to its false state at the same time since theC flip-flop was initially true. .The B ip-op remains true since it istriggered false only when A is false before the introduction' of` vtheclock signal. The operation of the A flip-dop in its false state and theB, C and D Hip-flops intheir true states represents a decimalvalu'e of2. This may be seen in Table XII(A).

In like manner,the A, Band C Hip-flops become triggered to differentpatterns of operation to represent the decimal values of `,3, f4xand,5.. YAs will berseen, the A, B and C ip-flops are in differentcombinations of true and false states for each value between 1 and 5,inclusive. When the A, B and C flip-flops are in states of operationindicative of a decimal value of 5, they return to a pattern ofoperation corresponding to a decimal value ,of l upon the introductionof the next clock signal. Inthis Way, the A, B and C flip-Hops operateon a recycling basis every time that five clock signals Cp areintroduced to the counter.

The D ip-op operates to provide a distinction between the'rst cycle ofoperation of the A, B and C flip-flops and the second cycle of operationof the A, B and'C'ip-llops. For example, the A, B and C flipflops havethe same pattern ofoperation forl the ydecimal functions.

value of "1 as for the decimal value of "6. However, the D flip-flop hasa false state of operation for the decimal value of 1 and a true state.of operation for the decimal value of 6. Because of this, the D flipopoperates to provide a distinction between values of 1 69,-

It will be seen from the above discussion that the A, B and C counteroperates to indicate a decimal scale of and the D counter operates toindicate a decimal scale of 2. By combining the two counters, acomposite counter having a decimal scale of l0 is obtained. Each decimalvalue in the scale-of-lO counter can be distinguished from every othervalue in the counter by connecting different output terminals in the A,B, C and D flip-flops to an and network. For example, for a decimalvalue of 8, an and network can receive output voltages from theterminals representing the true states of operation of the A and Dflip-flops and the terminals representing the false states of operationof the B and C flip-ops. Since the and network can pass a signal onlyupon the'simultaneous introduction of high voltages to all of its inputterminals, a signal can pass through the and network only for a decimalvalue of 8.

And circuits for providing the above-described operation are well knownin the computer art; suitable circuits, for example, being shown onpages 37 to 45 of High-Speed Computing Devices by Engineering ResearchAssociates, published in 1950 by McGraw-Hill Company, Inc., New York andLondon, and in an article entitled Diode coincidence and mixing circuitsin digital computers by Tung Chang Chen in vol. 38 of the Proceedings ofthe Institute of Radio Engineers, May 1950, on pgs. 511 through 514.

The scale-of-S counter defined by function set 5, above, is shown inFig. 3. The manner in which the and circuits shown in Fig. 3 provide theand functions: B Cp, v

C.Cp, .CD, A.Cp, and BCD should be apparent from the discussion above.It will be noted that the and c1rcu1t providing the changingtransformation function:

Cc=Cp is coupled to both the l and 0 input circuits of flip-flop C, sothat the pulse produced, when B is equal to l and a count pulse isapplied, is effective to trigger flip-flop C to its oppositerepresenting state.

Before proceeding to consider the transformation functions deiiningrepresentative types of 4-ip-flop counters, and the associated sequencetables, it is convenient to develop a simpler approach for obtaining asequence table directly from a set of simplified transformation It hasbeen shown that the changing transformation function:

defines a transformation of flip-op F such that its signal F', producedafter transformation, is related to the signals F and F, produced beforethe transformation by the function:

and that the changing function Cf may be simplified to the functions:

0F=H .Cp

Whenever flip-op F is in a O-representing state, wherel-representingstate wherein signals F and F have values 1 and 0, respectively, thefunction for F may be reduced to: F'=; indicating that wheneverflip-flop F was previously set to 1, it is transformed to the complementof signal H.

As an example of an application of the simplified approach discussedabove, consider the transformations shown in Table XIII, where flip-flopF is transformed according to the functions:

1F=G.Cp 0F=H.Cp

TableXIlI F G E F Row 0 o 0 o 1 1 0 0 1 2 o 1 0 1 3 1 1 0 1 4 It will benoted that signal F is 0, in rows 1 and 3, and that in these rows F isequal to the corresponding signal G. Thus, in row l: F=0, and F'=G=0. Fis equal to 1 in rows 2 and 4 and, in these rows, F is equal to thecorresponding complement of signal H. Thus, in row 2, F is equal to l,and F=1=1.

Consider now the sequence table for a 4-tlip-op, scale-of-9 counterdefined by the transformation function set:

A B' C' D Sequence It will be noted that whenever A is 0 it istransformed to the corresponding C signal and that whenever A is l it istransformed to the complement of the corresponding D signal. Thetransformation of signals B and C should be apparent from the discussionabove. While the transformation function for flip-flop D has been leftin its changing transformation form, indicating the mechanizationrequired, it may also be written as:

indicating that whenever D is 0 it is transformed to C, and that when Dis 1, it is transformed to C.

Although there are a considerable number of 4-flipflop countersaccording to the present invention, for simplicity, only a few of thebasic types are considered. The counters considered have cycles of 8,10, 11, 13, 15, and 16 and are mechanized, respectively, according tothe transformation sets:

condition, indicating that D is' always complemented when C is equal to0, except when A is and B is 1. Thus, the function Cd=C.Cp becomes: i

:n 5 J- 0A -D.C'p 0B A.Cp 0C B.Cp Cd=C.(AB)ICP=C(A+B)Cp (3) In a similarmanner, set 6 is obtained by interchanging 1 :0 0 1B=A C 1C=B,Ctransformed counts 1.(0010) and 1' (0011), defined by A p p p Cd: C Cp1o set 1. The interchangmg of these counts adds two change conditions tothe function: Cd=B.Cp; one change being OA-D'Cp OB-A'Cp 0C B'Cp addedafter each of the reference counts 0000, and 0001.

Thus, Cd becomes: (4) 15 Y 1A=C.Cp 1B=A.Cp 1U=B.C'p Cd=(B{-1.l: C`.D.l-A.B.C.l2)p

;Cd= C(A|B)C'p =(B|A.B.C).Cp=(B-|A.c).cp 0A =D.Cp 0B= A.Cp 0C= B.Cp

20 The scale-of-16 counter shown in Fig. 4 is mechanized according toset 6 in a manner very similar to the mech- (5) v an1zat1on ofscale-of-l() and the scale-of-8 counters shown 1A=C,Cp 1B=A.Cp 1C=BCp inFigs. 2 and 3, exceptv for the circuit controlling ip- Cd= 0-011 nop D.0A=D.Cp 0B=A.Cp 0C'= B.Cp 25 Referring now to Fig. 4, it will be notedthat a signal corresponding to the input function for flip-flop D, 6 Cd:(B-l-A.C),.Cp is produced by and circuit 410, having count pulse signalsCp applied to one input termi- 1A=C'.C'p 1B=A.C'p nal and a signalcorresponding to B-i-A.C applied to the Cc=B.Cp; Cd= (B+ A-C-P 30 otherinput terminal. The signal corresponding to 0A=DCp 0B=A-CP B-lisproduced by or circuit 420 which responds The counting sequences definedby these transformation t0 Signals B and A-C applied t0 Separate inputterminals. sets are shown in Table XV: Or circuit 420 produces ahigh-level output slgnal Table XV Set (1) set (2) sot (a) Set (4) ser(5) set (6) ABCD ABCD Seq. ABCD Seq. ABCD Seq. ABCD Seq. ABCD Seq. ABCDSeq.

388i 33t? l' 8835 lf 833? L 0000 2f 0101 n 0010 0 0100 0001 s' 0011 a"0010 11 0010 13 0110 2 0001 s iggi) iii digi) (gigi) 2 0100 12 0001 100111 3 The manner in Which the Sequences fOr Seis 1, v3, 40 lwhenevereither or both of signals B and E are highand 6 are Obtained Should beapparent from th? examples level signals. Finally, the function A C. isprovided by already considered. The scale-of-13 counter 1s obtainedaand, circuit 430. by combining the Cycles 0f 3 and. 10 defined Set 2iOr circuits suitable for providing the above-deand the Scale'0f`16counter 1S Obtamed by Combmmg the 60 scribed operation are described inthe above-mentioned iWO yles 0f 8 delled by Set 1- publications referredto as showing and circuits.

The Cycles 0f 3 and 10 defined by Set 2 are combined It should beapparent from the foregoing description by interchanging two transformedcounts, one from each that the present invention may be utilized toprovide cycle In the Pad'tiular Case defled by Set 5 count 3 countershaving any cycle desired Within the capacity of of the 3 cycle isinterchanged w1th count 10 of the l() 65 the number of ip 0ps included.It Should be under cycle- Transformed Count 3" 1s 0011 (retummg the? 3stood, then, that the S-ip-op transformation sets and Cycle i0 1") andtransformed CQUD 10 1S 0010 (,fetummg sequence table shown below areincluded only by way of the 10 Cycle to l) So.that,the mterchange-of 3,and 10 interest and are not intended to limit the scope of the causesonly a change m The change m D remves invention. Sets 1, 2, 3, and 4shown below definecounttwo of the changing condltions defined by thefunctlon: ers including cycles of 17! 29! 31, and 32, respectively.Cd=CCP Since D is no longer changed after the ref' The scale-of-32counter is obtained by combining the 29 erence counts 0100, or 0101. Thechange after lt l1ese and 3 cycles, defined by set 2y by interchangingtranscounts may be eliminated from the function: Cd=CCP formed counts11000 and 11001, thus changing the func- 'by adding the algebraicrestriction: B, as an and 75 tion: Ce=D.Cp to Cc= (D-|-A.B.C),Cp.

Table XVI (1) 2 3 4 ABCDE ABCDE Seq. ABCDE Seq. ABCDE Seq. ABCDE Seq.

The scale-of-32. counter shown in Fig. 5 is mechanized according totransformation set 4, above. Since the mechanizations of severalcounters according to transformation functions have already beenconsidered, it is believed that a detailed description of the circuitshown in Fig. 5 is unnecessary and is therefore omitted.

It has been explained above that many counting cycles may be obtainedfrom a few basic counters according to the present invention bycombining a rst counter having a rst counting cycle and a second counterhaving the first counting cycle or a second counting cycle. The secondcounting cycle may have no relationship to the rst counting cycle, Forexample, a scale-of-lO counter is shown in Figure 2. As previouslydescribed, this scaleof-lO counter is obtained by combining a counterhaving a counting cycle of 5 and a counter having a counting cycle of"2. Another technique for obtaining a variety of cyclesfrom a fewcounters of the type described above is to connect the counters into achain or into cascade In this type of circuit cach counter may beconsidered to be similar to the scale-of-Z counter in a binary chain.Whenever the counter is caused to complete its cycle and return to itsinitial stable state it produces a carry signal which is applied to thenext counter in the chain.

If the counter which is to be connected in cascade includes a flip-flopwhich is only changed twice during its cycle the carry signals may bederived from one section of this Hip-flop in the same manner as carrysignals are derived in prior-art binary, cascaded counters. Thus, whenthe scale-of-3 and scale-of-S counters described above are utilized incascaded counter chains, carry signals may be derived from a singleflip-flop of each counter, the particular ip-ilop undergoing only twochanges during a cycle. The counters utilized in chains must, of course,be preset so that the carry signals occur at the ends of the respectivecounting cycles.

The disadvantage of cascading counters due to the delay in propagatingcarry signals is considerably reduced when high-speed counters of thetype described in this application and the copending applications areutilized.

21 since the desired counting cycle may be obtained by cascading only afew counters.

22 pending application and set 2 being defined according to the presentinvention: i

1A =D.Cp

It is apparent, then, that with a few basic types of counters it ispossible to obtain a great number of cycles, by combining cycles,simultaneously operating counters, or by connecting counters intocascade. With five ipops, for example, it is possible to obtain any ofthe cycles 16 through 32; cycles of 19 and 23 being obtained bycombining other cycles such as 17 and 2 for 19, cycles including odd andeven factors having no common factor being obtained by simultaneouslyoperating the corresponding counters, and cycles including two odd ortwo even factors being obtained by cascading the corresponding counters.

From the foregoing discussion, it should now be understood that countershaving minimum gating circuits, may be mechanized according to thetransformation function: Cfr-G-t-FH, which may also be considered asdefining the relationship: F=F.G.}F.H. Where it is also desired thatfunction Cf define a minimum load for the ilip-ops in the counter, theonly restriction which is added is that signals G and H must bedifferent for each of the transformation functions in the defining set.This means that no Hip-op signal is used more than once, or that someflip-flop signals may not be utilized at all.

The scale-of-lO counter shown in Fig. 2 of this speciciication is onewhich includes all minimum gating circuits and provides a minimumloading for the ip-ops. It is interesting to compare the Hip-floploading of this counter with the scale-of-lO counter shown in the secondcopending application. The 10 counter of the copending application isdefined by the functions:

and the 10 counter of the present invention is defined by the functions:

It will be noted that in the transformation functions de iining the lcounter of the copending application, signal A is utilized four timesand signals B and C are utilized twice; whereas in the transformationfunctions defining the counter of the present invention signals A, B,and C are utilized only once. The section of flip-hop A in the 10counter of the copending application, then, must support four times theload that is required for any of the sections of the flip-flops in the10 counter of the present invention.

According to the definition of minimum gating circuits and minimumip-iop loading adopted above, a counter which is obtained by combiningtwo cycles in the abovedescribed manner cannot have all minimum gatingcircuits and cannot have minimum flip-flop loading, since at least onegating circuit is responsive to more than one signal and at least oneflip-flop signal is used twice. However, such a counter may provide muchsimpler gating and ip-op loading than a similar counter of the typedescribed in either the iirst or second copending application. Forexample, compare the scale-of-32 counters defined by function sets 1 and2 below; set 1 being defined according to the principles set forth inthe first co- In set 1 signal A is utilized four times; whereas in set 2no signal is used more than twice, signals A, B, D, D, and E being usedonly once.

While the principal object of the present invention is to provideminimum gating `circuit flip-op counters wherein the ip-op load is wellbalanced and in some cases a minimum load; it is apparent that theinvention is` generic to all counters which may be obtained from thebasic counters by combining cycles, simultaneously operating counters,or cascading counting stages.

Although only a relatively few species of the present invention havebeen shown in the figures and described throughout the specification, itis apparent that the principles herein developed may be extended tocounters utilizing any number of Hip-flops, for obtaining any cycledesired.

What is claimed is:

1. An N-stage electronic counter for producing countrepresenting signalscorresponding to the number of previously-applied count pulses Cp thestages in the counter having different combinations of operation torepresent different values and having a number of combinations ofoperation greater than the number of stages in the counter, saidelectronic counter comprising: dip-lop designated as A, B and N, eachincluding a l and a 0 input circuit and producing complementaryvoltagestate signals designated as A, A and B, and

N, N, respectively; and transformation matrix means coupled to saidinput circuits and responsive to said voltage-state signals and to countpulses Cp for producing control signals for actuating said Hip-hops tochange said complementary voltage-state signals according to apredetermined sequence, said transformation matrix means being connectedto produce control signals for actuating the different flip-Hops inaccordance with transformation functions at least two of which aredefinable as Where F and F respectively represent true and false statesof operation of one of the ip-flops in the counter and designated as theF flip-flop, where G and H represent voltages from flip-flops in thecounter other than the F flip-hop, where Cf represents a signal fortriggering the F flip-Hop from the true state of operation to the falsestate of operation or from the false state of operation to the truestate of operation, where Cp represents the clock signals, where the dotrepresents an and relationship, and where the plus sign represents an orrelationship.

2. In an electronic counter for counting the number of applied countpulses designated as Cp and indicating the count in the form of abinary-coded number, the combination comprising: Hip-flops designated asA, B and N, each including a 1 and a 0 nputcircuit and producingcomplementary voltage-state signals designated as A, and B, and N, N,respectively; and transformation matrix means coupled to said inputcircuits and responsive to said voltage-state signals and to said countpulses Cp for producing pairs of control signals for introduction to theinput circuits of the dilerent flipllops, the transformation matrixmeans being coupled to at least two pairs of said input circuits inaccordance with 23 the following functions for one of the pairs ofvinput circuits 1F=G.Cp F=H.Cp

where 1F and OF respectively' represent the introduction of inputsignals to the 1 and 0 input circuits of a flip-Hop designated as the Fflip-flop, where Cp represents the pulses to be counted, where G and Hrespectively represent voltage-state output signals from ip-ops in thecounter other than the F flip-nop, and where the dot represents an andrelationship.

3. In a flip-flop counter for counting the number of applied countpulses Cp, the combination comprising: N ip-flops, each including a 1and a 0 input circuit and producing a pair of complementary outputsignals; and transformation matrix means coupled to said input circuitsand responsive to said output signals and to said count pulses Cp forproducing pairs of control signals for actuating said flip-flops tochange said output signals according to a predetermined sequence, saidtransformation matrix means including N pairs of gating circuits coupledto the input circuits of said N flip-flops, respectively, said gatingcircuits producing pairs of said control signals according to one of aplurality of transformation functions at least two of which arerepresentable as where F and F represent the complementary outputsignals produced by one of the ilip-ops to be controlled and designatedas the F Hip-flop, where each of G and H represents the outputsignalsfrom only one ip-op in the` counter other than the F ip-op, WhereCf represents the introduction of a control signal to the gatingcircuits of the F flip-flop, where Cp represents the pulses to becounted, where the dot represents an and relationship, and where theplus sign represents an or relationship.

4. A multistage ybinary-coded counter for counting the number of appliedcount pulses Cpy the stages in the counter having different combinationsof operation to represent different values and having a number ofcombinations of operation greater than the number of stages in thecounter, comprising; a plurality of ip-o-ps, each including. a pair ofinput circuits and producing a pair of complementary voltage-statesignals; and matrix means coupled to said input circuits :and responsiveto said voltage-state signals andl to said count pulses Cp for producingpairs of control signals, one pair for each flip-flop, `for actuatingsaid flip-ops to change said complementary voltage-state signalsaccording to a predetermined sequence, said matrix means including aplurality of pairs of gating circuits coupled to the input circuits ofsaid Hip-flops, respectively, each of said gating circuits applying acontrol signal to one input circuit of the associated vflip-flop andbeing mechanized for co-ntrol by a maximum of onlyv one of thevoltage-state signals other than the ip-op receiving the signals fromthe gating circuit.

5. In an electronic counter for counting the number of applied countpulses designated as Cp and indicating the count in the form of abinary-coded number, the combination comprising: a plurality of ilip-opsdesignated as A, B, and N, each including a 1 and a 0 input circuit andproducing complementary voltage-state` signals designated as A, A and B,B, and N, N, respectively; and transformation matrix means coupled tosaid input circuits and responsive to said voltage-state signals and tosaid count pulses Cp for producing control signals for application toeach ip-op in accordance with the changing transformation functionwhereF and F represent the complementary voltage-state signals producedby one of the flip-flops in the counter designated as theA F ip-flop,where G and H represent voltage-state signals produced by other ilip-opsin the counter than the F Hip-flop, where Cf represents signals passingthrough the transformation matrix means to the input circuits of the Fflip-flop, where Cp represents the pulses to -be counted, where the dotrepresents an and relationship, and where the plus sign represents an orrelationship.

6. A binary-coded, scale-of-IO counter comprising: four ip-ops, eachincluding a 1 and a 0 input circuit and producing a pair ofcomplementary output signals; and transformation matrix means coupled tosaid input circuits and responsive to said output signals and to appliedcount pulses for producing control signals for actuating said flip-flopsto produce distinctive patterns of operation of the ip-ops for anindividual count of the pulses between l and "10, said transformationmatrix means including eight gating circuits coupled to `said `inputcircuits, respectively, each of said gating circuits applying a controlsignal to the associated ip-op input circuit in accordance with anoutput voltage from a different one of the flip-ops in the counter otherthan the associated flip-op for the application of each output voltagefrom the different flip-flops to at most only one of the gatingcircuits.

7. The binary-coded, scale-of-l() counter defined in claim 6, in whichiive gating circuits apply signals to the associated flip-flop inputcircuits upon only the occurrence of count pulses and the other threegating circuits are and networks each receiving the count pulses and theoutput signals from one of the flip-Hops other than the ip-op associatedwith the gating circuit.

8. The binary-coded, scale-of-lO counted defined in claim 6 wherein `thefour flip-flops are designated as A, B, C and D; wherein the pairs ofcomplementary output signals from the A, B, C and D flip-ilops arerespectively designated as A and B and B., C and C and D and D; andwherein the eight gating circuits are mechanized as where 1A, 1B, 1C and1D respectively represent the introduction of control signals to the linput circuits of the A, B, `C and D flip-flops, where 0A, 0B, 0C and 0D`respectively represent the introduction of control signals to the 0input circuits of the A, B, C and -D ip-ops, where Cp represents thepulses to be counted, and where the dot represents an and relationship.

9. A binary-coded, scale-of-8 counter comprising: three ip-flops A, B,and C, producing pairs of complementary output signals A, A; B, B; andC, C; respectively, each flip-flop including a l and a O input circuit;and trans formation matrix means coupled to said input circuits andresponsive to said output signals and to applied count pulses Cp forproducing three corresponding pairs of control signals for actuatingsaid flip-flops to change said output signals according to a scale-of-Ssequence, one pair of said control signals being applied to the l and 0input circuits, respectively, of each of flip-flops A, B, and C, `saidpairs of control signals being defined, respectively, by :thetransformation functions:

1A=B.Cp 1B=A-Cp Cc=B-Cp 0A=C-Cp 0B=A-Cp where 1A and 1B respectivelyrepresent the introduction of control signals to the l input circuits ofthe A and B flip-flops, where 0A and OB respectively represent theintroduction of control signals to the 0 input circuits of the A and Bilip-ops, where Cc represents signals introduced to flip-op C and wherethe dot represents an and relationship.

10. A ybinary-coded, scale-of-S counter comprising:

three Hip-flops designated as A, B-,f-and C, producingpairs of.complementary Output signals designated as A, inputocircuits of the Cdip-flop, where Cd represents sig- B and C E; respectively each ip opincluding a nals lntroduced to the lnput circtuts of the D flip-flop, 1and a 0 input circuit; and transformation matrix means Where the dotIepesents an and feltwnslilp aild coupled to said input circuits andresponsive to said out- Where the mus Hr) slgn represents an orrelanorihlp put signals and to applied count pulses designated as Cp 512' .A bmary'coded Sca1e'0f'3 2 counter .COmpr.1smg: for producing threepairs of control signals for actuating ve lp'ops A B C. D and .E poduclgpigs of said Hip-flops to produce distinctive patterns of operationeorrliulementary Output Slgnals A A; B B5 C: C? D: D3 and of theip-flops for an individual count of the count pulses E, E; respectively,each ip-op including a 1 and a 0 lbetween 1 and 5 in accordance with thetransformainput circuit; and transformation matrix means coupled tionfunctions: v to said input circuits and responsive to said outputsignals and to applied count pulses Cp for reducing ve correlAzp 1B=p1C: Cp sponding pairs of control signals foi actuating said ipwhere 1A,1B and 1C respectively represent the introduction of control signals tothe 1 input circuits of the A, B `and C ilip-flops, where 0A, 0B and 0Crespectively represent the introduction of control signals to the 0input `of-32 sequence, one pair of said control signals being applied tothe 1 and 0 input circuits, respectively, of each of flip-flops A, B, C,D, and E, said pairs of control signals being defined, respectively, bythe transformation functions:

1A=D.Cp 1B=0p 10=B.Cp 1D=C'.Cp

,'Ce=(D-|A.B.C').Cp 0A=E.Cp 0B=A.Cp 0C'=B.Cp 0D= C'.Cp circuits of theA, B and C ip-flops, and Where the dot Where 1A, 1B, 1C and 1Drespectively represent signals represents `an and relationship.introduced to the l input circuits of the A, B, C and D 1l. Abinarycoded, scale-of-16 counter comprising: flip-Hops, where 0A, 0B, 0Cand 0D respectively reprefour flip-flops A, B, C, and D, producingpair-s of comsent signals introduced to the 0 input circuits of the A,B, plementary Output Signals A, B, C, E; and D, '15; C and Hip-flops,Where Ce represents signals introduced respectively, each flip-flopincluding a 1 and' a 0 input 30 te the mput erreurfs 0f trie E rP'ePWhere the dot (J circuit; and transformation matrix means coupled tosaid t represents an and relanonsprp eind Where the Plus input circuitsand responsive to said output signals and srgn represents an orrelatlonshrpto applied count pulses Cp for producing four correspondingpairs of control signals for actuating said ip-ops to References Cited mthe me of thls patent change said output signals according to ascale-of-16 se- 35 UNITED STATES PATENTS quence, one pair of saidcontrol signals Ibeing applied to the 1 and 0 input circuits,respectively, of each of ip- 215361955 Palmer et al- Jarr- 2 1951 ops A,B, C, and D, said pairs of control signals being 2,584,363 Mumrna Feb 51952 defined, respectively, by the transformation functions: 2,630,969Sehmldt Mar- 10 1953 2,715,678 Barney Aug. 16, 1955 1A=C-Up 1B=ACp 402,719,670 Jacobs et a1. ocr. 4, 1955 Cc=B.Cp; Cd= (B-l-A-C).Up 2,758,788Yeager Aug. 14, 1956 0A =D.Cp OB='.Cp 2,764,343 Diener Sept. 25, 1956where 1A and 1B respectively represent control signals introduced to the1 input circuits of the A and B ip- 45 flops, where 0A and 0Brespectively represent c-ontrol signals introduced to the O inputcircuits of the A and B tlip-ops, where Cc represents signals introducedto the OTHER REFERENCES The Physical Realization of an ElectronicDigital Computer,'by A. D. Booth, Electronic Engineering (British),ADecember 1950, pages 492-496.

ops to change said output signals according to a scale- UNITED STATESPATENT @Trier CERTIFICATE 0F C() i ECHGN Patent Nm 298535238 September23, i958 Robert Boyce Jomeon It is hereby certified that error appearsin the printed specification of the above numbered patent requiringcorrection and that the said Letters Patent should read as correctedbelow.

Colmn L, line 64, for toet portion of the equation reading reed w Fmgddelumn o, line 6g for that portion of the equation reading "S130"read 45m n; column lip lin@ O for tiret portion of the equation readinglBAoCp'Y read ma iBS-*xp Signed amd sealed this 27th dey of January19590 Attest:

KARL H0 y AYLNE Attcsting Officer ROBERT C. WATSON Commissioner ofPatents

